A semiconductor transistor device is a device comprising a gate which interconnects a pair of source/drain regions with one another through a channel controlled by the gate. Transistor devices are common circuit devices of semiconductor constructions. For instance transistor devices can be incorporated into memory structures, including, for example, dynamic random access memory (DRAM) and static random access memory (SRAM).
A continuing goal in semiconductor fabrication is to increase a level of integration, and thus decrease the amount of semiconductor real-estate consumed by devices. Decreasing the size of transistor devices, however, leads to numerous difficulties. For instance, as the channel-length of a transistor device is decreased, numerous problems occur in attempting to control electron flow between source/drain regions on opposing sides of the channel. These problems are generically referred to as short-channel effects.
One approach that may have utility for overcoming short-channel problems is to recess transistor devices within a substrate so that the devices consume less real-estate than if they were non-recessed, and yet have relatively long channels. A non-recessed (i.e., planar) transistor device is shown in FIG. 1, and a recessed device is shown in FIG. 2 for comparison to the non-recessed device.
Referring initially to FIG. 1, a semiconductor construction 10 is illustrated to comprise a substrate 12. The substrate 12 can comprise, for example, monocrystalline silicon lightly-doped with background p-type dopant. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A transistor device 14 is supported by the substrate. The transistor device includes a gate 16 spaced from substrate 12 by a dielectric material 18; includes sidewall spacers 24 along sidewalls of the gate; includes a pair of source/drain regions 20 on opposing sides of the gate; and includes a channel region 22 between the source/drain regions.
The gate 16 can comprise various electrically conductive materials, including, for example, various metals, metal compositions, and/or conductively-doped silicon or other conductively-doped semiconductor material. Dielectric material 18 can comprise any suitable material or combination of materials, and typically will comprise, consist essentially of, or consist of silicon dioxide. Sidewall spacers 24 can comprise any suitable compositions or combination of compositions, and typically will comprise one or both of silicon nitride and silicon dioxide. Source/drain regions 20 can comprise conductively-doped regions within monocrystalline substrate 12, and can comprise heavily-doped regions with lightly-doped extensions. For instance, the source/drain regions 20 can comprise either heavily n-type doped regions or heavily p-type doped regions, and can comprise lightly-doped portions extending under sidewalls 24. Channel region 22 is doped with a threshold voltage implant, and operably interconnects the source/drain regions 20 with one another when sufficient current passes through gate 16.
FIG. 2 shows a construction 30 comprising a semiconductor substrate 32 and a transistor 34 supported by the substrate. The transistor comprises a gate 36 extending within the substrate, a dielectric material 38 between the gate and the substrate, source/drain regions 40 within the substrate proximate the gate, and a channel region 42 extending around a lowermost portion of the gate and interconnecting the source/drain regions 40 with one another. Although not shown, sidewall spacers can be provided proximate gate 36 similar to the spacers 24 discussed above with reference to FIG. 1.
The substrate 32, dielectric material 38, gate 36 and source/drain regions 40 can comprise identical materials to those discussed above regarding the substrate 12, gate 16, dielectric material 18 and source/drain regions 20 of FIG. 1. Also, a threshold voltage implant can be provided within channel region 42 similar to the threshold voltage implant provided within region 22 of FIG. 1.
A difference between the recessed device construction of FIG. 2 relative to the non-recessed device construction of FIG. 1 is that the channel region 42 of the device of FIG. 2 is lengthened by virtue of the channel region extending around a recessed portion of the gate 36. Such can reduce short-channel effects for the transistor device 34 of FIG. 2 relative to the device 14 of FIG. 1.
Although recessed access devices have advantages relative to non-recessed devices in terms of the packing density that can be achieved while avoiding short-channel effects, there are various problems encountered in large-scale fabrication of recessed access devices which are to be addressed if recessed access devices are to become commercially feasible. Accordingly, it is desired to develop new methodology for large-scale fabrication of recessed access devices. One application for recessed access devices is in memory arrays, such as, for example, DRAM arrays. Accordingly, it would be further desirable if methodologies developed for large-scale fabrication of recessed access devices were applicable to fabrication of memory arrays.